Based on the analysis of the system architecture of scaler chip used in flat panel displayer, three constraints were proposed: the output frame rate must be same as the input frame rate of the scaler, no overflow and underflow in asynchronous FIFO(first in first out), no overflow and underflow in line buffer.
当满足这三个约束条件时 ,定标器中的FIFO和行缓冲区不会上溢或下溢 ,显示帧与输入帧同步 ,解决了定标器的时序问题 。
本网站所收集内容来自网友分享仅供参考，实际请以各学校实际公布信息为主！内容侵权及错误投诉：1553292129@qq.com
CopyRight © 2020-2024 优校网[www.youxiaow.com]版权所有 All Rights Reserved. ICP备案号：浙ICP备2024058711号